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STLVDS9637
HIGH SPEED DIFFERENTIAL LINE RECEIVERS
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MEETS OR EXCEEDS THE REQUIREMENTS OF ANSI TIA/EIA-644 STANDARD OPERATES WITH A SINGLE 3.3V SUPPLY DESIGNED FOR SIGNALING RATE UP TO 400Mbps DIFFERENTIAL INPUT THRESHOLDS 100mV MAX TYPICAL PROPAGATION DELAY TIME OF 2.5ns POWER DISSIPATION 60mW TYPICAL PER RECEIVER AT 200MHz LOW VOLATGE TTL (LVTTL) LOGIC OUTPUT LEVELS OPEN CIRCUIT FAIL SAFE ESD PROTECTION: 7KV RECEIVER PINS 3KV ALL PINS VS GND
SOP
DESCRIPTION The STLVDS9637, is a differential line receiver that implements the electrical characteristics of low voltage differential signaling (LVDS). This signaling technique lowers the output voltage levels of 5V differential standard levels (such as TIA/EIA-422B) to reduce the power, increase the switching speeds and allow operations with a 3.3V supply rail. This differential receiver provides a ORDERING CODES
Type STLVDS9637BD STLVDS9637BDR Temperature Range -40 to 85 C -40 to 85 C
valid logical output state with a 3.3V supply rail. It also provides a valid logical output state with a 100mV differential input voltage within the input common mode voltage range. The input common mode voltage allows 1V of ground potential difference between two LVDS nodes. The intended application of this device and signalling technique is both point-to-point and multidrop data transmission over controlled impedance media approximately 100. The transmission media may be printed circuit board traces, backplanes or cables. The ultimate rate and distance of data transfer depend upon the attenuation characteristics of the media and noise coupling to the environment. The STLVDS9637 version is characterized for operation from -40C to 85C.
Package SO-8 (Tube) SO-8 (Tape & Reel)
Comments 100parts per tube / 40tube per box 2500 parts per reel
May 2003
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STLVDS9637
PIN CONFIGURATION
PIN DESCRIPTION
PlN N 2, 3 5, 7 6, 8 4 1 SYMBOL 1Y to 2Y 1B to 2B 1A to 2A GND VCC NAME AND FUNCTION Receiver Outputs Negated Receiver Inputs Receiver Inputs Ground Supply Voltage
LOGIC DIAGRAM AND LOGIC SYMBOL
TRUTH TABLE
DIFFERENTIAL INPUTS A, B VID 100mV -100mV < VID < 100mV VID -100mV OPEN
L = Low level, H = High Level, X = Don't care, Z = High Impedance, ? = Indeterminate
OUTPUT Y H ? L H
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STLVDS9637
ABSOLUTE MAXIMUM RATINGS
Symbol VCC VI VI ESD Tstg Supply Voltage (Note 1) Input Voltage Input Voltage (A or B inputs) Human Body Model Storage Temperature Range Pins Receivers All Pins vs GND Parameter Value -0.5 to 4.6 -0.5 to (VCC + 0.5) -0.5 to 4.6 7 3 -65 to +150 Unit V V V KV C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied. Note 1: All voltages except differential I/O bus voltage, are with respect to the network ground terminal.
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VIH VIL |VID| VIC TA Supply Voltage HIGH Level Input Voltage (ENABLE) LOW Level Input Voltage (ENABLE) Magnitude of Differential Input Voltage Common Mode Input Voltage Operating Temperature Range 0.1 0.5|VID| -40 Parameter Min. 3.0 2.0 0.8 0.6 2.4-0.5|VID| VCC - 0.8 85 C Typ. 3.3 Max. 3.6 Unit V V V V V
ELECTRICAL CHARACTERISTICS (Over recommended operating conditions unless otherwise noted. All typical values are at TA = 25C, and VCC = 3.3V)
Symbol VITH+ VITHVOH VOL ICC ICC II II(OFF) IIH IIL IOZ Parameter Positive Going Differential Input Voltage Threshold Negative Going Differential Input Voltage Threshold High Level Output Voltage Low Level Output Voltage Supply Current for STLVDS32, STLVDS3486 Test Conditions Min. Typ. Max. 100 -100 IOH = -8mA IOH = -4mA IOH = 8mA Enabled, No Load Disabled No Load -2 -1.2 VI = 3.6V 10 0.25 4 -10 -3 10 20 10 10 10 A A A A 2.4 2.8 0.4 18 0.5 10 -20 V mA mA mA A Unit mV mV V
Supply Current for STLVDS9637 Input Current (A or B inputs) VI = 0V Power off Input Current (A or B inputs) High Level Input Current (EN, G, G or Inputs) Low Level Input Current (EN, G, G or Inputs) High Impedance Output Current
VI = 2.4V VCC = 0 VIH = 2V VIL = 0.8V VO = 0 or VCC
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STLVDS9637
SWITCHING CHARACTERISTICS (Unless otherwise noted. Typical values are referred to TA = 25C and VCC = 3.3V)
Symbol tPLH tPHL tr tf tsk(O) tsk(P) tsk(PP) tPZH Parameter Propagation Delay Time, CL = 10pF Low to High Output Propagation Delay Time, High to Low Output Differential Output Signal Rise Time Differential Output Signal Fall Time Channel to Channel Output Skew (note1) Pulse Skew (|tPHL - tPLH|) (note2) Part to Part Skew (note3) Propagation Delay Time, High Impedance to High Level Output Propagation Delay Time, High Impedance to Low Level Output Propagation Delay Time, High Level to High Impedance Output Propagation Delay Time, Low Level to High Impedance Output Fig. 2 Test Conditions Fig. 1 Min. 1.5 1.5 Typ. 2.5 2.5 0.4 0.4 0.1 0.2 0.3 0.4 1 3 12 Max. 3.3 3.3 Unit ns ns ns ns ns ns ns ns
tPZL
5
12
ns
tPHZ
5
12
ns
tPLZ
5
12
ns
Note 1: tsk(O) is the maximum delay time difference between the propagation delay of one channel and that of the others on the same chip with any event on the inputs. Note 2: tsk(P) is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of the same channel. Note 3: tsk(PP) is the differential channel-to-channel skew of any event between devices. This specification applies to devices at the same VCC, and within 5C of each other within the operating temperature range.
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STLVDS9637
Figure 1 : Timing Test Circuit, Timing And Waveforms
Note A: All input pulse are supplied by a generator having the following characteristics: tr or tf 1ns, pulse repetition rate (PRR) = 50Mpps, pulse width = 10 0.2ns. Note B: CL includes instrumentation and fixture capacitance within 6mm of the D.U.T.
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STLVDS9637
Figure 2 : Enable And Disable Time Test Circuit And Waveform
Note A: All input pulse are supplied by a generator having the following characteristics: tr or tf 1ns, pulse repetition rate (PRR) = 50Mpps, pulse width = 500 10ns. Note B: CL includes instrumentation and fixture capacitance within 6mm of the D.U.T.
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STLVDS9637
TYPICAL PERFORMANCE CHARACTERISTICS (unless otherwise specified Tj = 25C) Figure 3 : Output Current vs Output Voltage Figure 4 : Output Current vs Output Voltage
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STLVDS9637
SO-8 MECHANICAL DATA
DIM. A A1 A2 B C D E e H h L k ddd 0.1 5.80 0.25 0.40 mm. MIN. 1.35 0.10 1.10 0.33 0.19 4.80 3.80 1.27 6.20 0.50 1.27 8 (max.) 0.04 0.228 0.010 0.016 TYP MAX. 1.75 0.25 1.65 0.51 0.25 5.00 4.00 MIN. 0.053 0.04 0.043 0.013 0.007 0.189 0.150 0.050 0.244 0.020 0.050 inch TYP. MAX. 0.069 0.010 0.065 0.020 0.010 0.197 0.157
0016023/C
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STLVDS9637
Tape & Reel SO-8 MECHANICAL DATA
mm. DIM. MIN. A C D N T Ao Bo Ko Po P 8.1 5.5 2.1 3.9 7.9 12.8 20.2 60 22.4 8.5 5.9 2.3 4.1 8.1 0.319 0.216 0.082 0.153 0.311 TYP MAX. 330 13.2 0.504 0.795 2.362 0.882 0.335 0.232 0.090 0.161 0.319 MIN. TYP. MAX. 12.992 0.519 inch
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STLVDS9637
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. (c) The ST logo is a registered trademark of STMicroelectronics (c) 2003 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. (c) http://www.st.com
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